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Journals

[1]

Chi-Chou Kao*, July 2019, “Design and Implementation of Stereoscopic Image Generation,” Journal of Circuit , Systems, and Computers (JCSC), Vol. 28, Issue 8,  pp. **-**. (SCIE, MOST 104-2221-E-024-001, ISSN: 0218-1266, doi: 10.1142/S0218126619501330)

[2]

Chi-Chou Kao*, February 2018, “Mapping Virtual Tasks onto Physical Devices for Cloud Computing,” Journal of Computers, Vol. 29 No. 1, pp. 40-46. (EI, ISSN: 1991-1599)

[3]

Chi-Chou Kao*, October 2017, “Improved Feature Extraction and Classification Methods for Electroencephalographic Signal based Brain-Computer Interfaces,” International Journal of Computers and Applications, Vol. 39, Issue 04, pp. 189-197. (EI, ISSN: 1206-212X)

[4]

Chi-Chou Kao* and Yi-Ciang Lin, July 2017, “Design of Low Power Snoop for Multi-Processor System on Chip,” Journal of Signal Processing Systems for Signal, Image, and Video Technology,  Vol. 88, Issue 1, pp 83–89. (SCIE, NSC 101-2221-E-024-017, ISSN: 1939-8018)

[5]

Chi-Chou Kao*, June 2017, “Stereoscopic Image Generation with Depth Image Based Rendering,” Multimedia Tools and Applications, Vol. 76, Number 11, pp. 12981-12999.  (SCI, MOST 104-2221-E-024-001, ISSN: 1573-7721)

[6]

Chi-Chou Kao*, August 2016, “Shape-Based 3D Model Retrieval System,” International Journal of Computers and Applications, Special Issue: Computational Intelligence and Communications, pp. 1-10. (EI, MOST 104-2221-E-024-001, ISSN: 1206-212X)

[7]

Chi-Chou Kao*, Yen-Tai Lai, and Chao-Feng Tseng, June 2016, “Improved Edge-Directed Super Resolution,” International Journal of Computers and Applications, Vol. 37, Issue 03-04, pp. 160-167. (EI, ISSN: 1206-212X)

[8]

Chi-Chou Kao*, April 2015, “Clock Skew Minimization in Multiple Dynamic Supply Voltage with Adjustable Delay Buffers Restriction,” Journal of Signal Processing Systems for Signal, Image, and Video Technology, Vol. 79, Issue 1, pp. 99-104.  (SCIE, NSC101-2221-E-024-020, ISSN: 1939-8018)

[9]

Chi-Chou Kao*, March 2015, “Performance-Oriented Partitioning for Task Scheduling of Parallel Reconfigurable Architectures,”  IEEE Transactions on Parallel and Distributed Systems (TPDS), Vol. 26, No. 3, pp. 858-867. (SCI, NSC 101-2221-E-024-017, ISSN: 1045-9219)

[10]

Chi-Chou Kao* and Wen-Lin Yang, April 2014, “Energy Efficient System-on-Chip Design for Wireless Body Area Sensor Network,” Electric Power Components and Systems (UEMP), Vol. 42, Issue 7, pp. 737-745. (SCIE, NSC 101-2221-E-024-020, ISSN: 1532-5008)

[11]

Chi-Chou Kao* and Yen-Tai Lai,  June 2013, “Improved Time-Multiplexed FPGA Architecture and Algorithm for Minimizing Communication Cost Designs,” Journal of Circuits, Systems, and Computers (JCSC), Vol. 22, No. 5, 1350033 (16 pages). (SCIE, NSC 95-2221-E-251-004, ISSN: 0218-1266)

[12]

Chi-Chou Kao*, March 2013, “Fast Intra Prediction Mode Decision for H.264/AVC Video Coding,” Imaging Science Journal (IMS), Vol. 61, No. 3, pp.311-319. (SCI, NSC 100-2221-E-024-010, ISSN: 1368-2199)

[13]

Chi-Chou Kao*, December 2012, “Design and Implementation of Car Navigation and Cockpit Infotainment Embedded System on Open Service Gateway initiative,” International Journal of Science and Engineering (IJSE), Vol.2, No4, pp. 25-30.  (NSC 100-2221-E-024-010, ISSN: 2223-4489)

[14]

Chi-Chou Kao*, July 2012, “Interface Circuit Synthesis of System-on-Chip,” International Journal of Electronics (IJE), Vol. 99, Issue 7, pp. 957–970. (SCI, NSC 97-2221-E-024-016, ISSN: 0020-7217)

[15]

Chi-Chou Kao*, September 2011, “BDD-Based Synthesis for Mixed COMS/PTL Logic,” International Journal of Circuit Theory and Applications (IJCTA), Vol. 39, Issue 9, pp. 923-932. (SCI, ISSN: 0098-9886 )

[16]

Chi-Chou Kao*, August 2011, “High Performance CORDIC Rotation  Algorithm Based on Look-Ahead Techniques,” International Journal of Electronics (IJE), Vol. 98, No. 8, pp. 1075-1089. (SCI, ISSN: 0020-7217)

[17]

Chi-Chou Kao*, Chia-Nan Yeh,  and Yen-Tai Lai, March 2011, “Low Energy Cluster-Head Selection for Clustering Communication Protocols in Wireless Sensor Network,” International Journal of Computers and Applications, Vol. 33, No. 1, pp. 9-14. (EI, ISSN: 1206-212X)

[18]

Wen-Lin Yang*, Chi-Chou Kao, and Cheng-Huang Tung, February 2011, “Heuristic Algorithms for Constructing Interference-free and Delay-Constrained Multicast Trees for Wireless Mesh Networks,” KSII Transactions on Internet and Information Systems (ITIIS), Vol. 5, No. 2, pp. 269-286. (SCIE, NSC-98-2221-E-024-004-MY2, ISSN: 1976-7277)

[19]

Chi-Chou Kao*, December 2010, “Performance-Driven Methods for Fine Granularity Scalable Video Coding,” International Journal of Computers and Applications, Vol. 32, No. 4, pp. 412-419. (EI, ISSN: 1206-212X)

[20]

Yen-Tai Lai, Chi-Chou Kao*, Tzu-Chiang Tai, and Wen-Chun Yeh, November 2010, “A Performance-Driven Rotational Invariant Image Retrieval System,” Journal of Information Science and Engineering (JISE), Vol. 26, No. 6, pp. 2009–2022. (SCIE, NSC 98-2221-E-024-005, ISSN: 1016-2364)

[21]

Chi-Chou Kao*, Yen-Tai Lai, and Chia-Hui Lin, June 2010, “An Efficient Reflection Invariance Region-Based Image Retrieval Framework,” International Journal of Imaging Systems and Technology (IJIST), Vol. 20, Issue 2, pp. 155–161. (SCIE, ISSN: 0899-9457)

[22]

Chi-Chou Kao*, Tzu-Chiang Tai, and Yen-Tai Lai, February 2010, “An Optimisation Communication Cost Algorithm for Dynamically Reconfigurable FPGAs,” International Journal of Electronics (IJE), Vol. 97, Issue 2, pp. 177–182. (SCI, ISSN: 0020-7217)

[23]

Chi-Chou Kao*, January 2008, “Computer-Aided Crosstalk Minimisation Design for System-on-Chip,” IET Computers and Digital Techniques (IET-CDT), Vol. 2, Issue 1, pp. 23–29. (SCIE, ISSN: 1751-8601)

[24]

Chi-Chou Kao*, February 2007, “A High Flexibility Design for Clock Distribution Network in System on Chip,” Journal of Circuits, Systems, and Computers (JCSC), Vol. 16, No. 1, pp. 51–63. (SCIE, ISSN: 0218-1266)

[25]

Chi-Chou Kao* and Chun-Chen Hsu, January 2007, “ALGA: Automated Layout Generator for Analog CMOS Circuits,” International Journal of Electronics (IJE), Vol. 94, Issue 1, pp. 81–97. (SCI, ISSN: 0020-7217)

[26]

Chi-Chou Kao* and Yen-Tai Lai, August 2006, “Design of Field Programmable Gate Arrays with Hierarchical Interconnection Structures,” International Journal of Electrical Engineering (IJEE), Vol. 13, No. 3, pp. 291–296. (EI,  NSC 95-2221-E-251-004, ISSN: 1812-3031)

[27]

Chi-Chou Kao*, Chuen-Yau Chen, and Yen-Tai Lai, May 2006, “A Spatiotemporal Unsupervised Segmentation Algorithm for Video on-Chip System,” Optical Engineering (OE), Vol. 45, pp. 057401–057408. (SCI, ISSN: 0091-3286)

[28]

Chi-Chou Kao*, Shih-Hwei Tang, and Ming-Hui Chan, April 2005, “Design of Interactive E-Learning System,” Journal of National University of Tainan, Vol. 39, No. 1, pp. 111–132. (ISSN: 1028-737X)

[29]

Chi-Chou Kao* and Yen-Tai Lai, January 2005, “An Efficient Algorithm for Finding the Minimal Area FPGA Technology Mapping,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 10, Issue 1, pp. 168–186. (SCIE, NSC 93-2215-E-251-001, ISSN: 1084-4309)

[30]

Chi-Chou Kao*, November 2003, “Design of Echo Cancellation and Noise Elimination for Speech Enhancement,” IEEE Transactions on Consumer Electronics (TCE), Vol. 49, Issue 4, pp. 1468–1473. (SCI, ISSN: 0098-3063)

[31]

Yen-Tai Lai and Chi-Chou Kao*, November 2002, “A Technology Mapping Algorithm for Heterogeneous FPGAs,” IEE Proceedings Computers and Digital Techniques (IEE-CDT), Vol. 149, Issue 6, pp. 249–255. (SCIE, ISSN: 1751-8601)

[32]

Chi-Chou Kao*, Lan Kuo, and Yen-Tai Lai, May 2002, “An Improved Three-Step-Search Algorithm for Block Matching Motion Estimation and Its ASIC Design,” Journal of Chinese Institute of Electrical Engineers (JCIEE), Vol. 9, No. 2, pp. 151–157. (EI, ISSN: 1812-3031)

[33]

Chi-Chou Kao* and Yen-Tai Lai, November 2001, “A Routability Driven Technology Mapping Algorithm for LUT Based FPGA Designs,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (IEICE-ECCS), Vol. E84-A, No. 11, pp. 2690–2696. (SCIE, ISSN: 0916-8508)

Conferences

[1]

Chi-Chou Kao* and Monica Tu, “Improved Depth-Image-Based Rendering System,” Asia-Pacific Conference on Engineering and Applied Science (APCEAS), pp. 473–484 (2016 August 25-27, Tokyo, Japan). (EI, MOST 104-2221-E-024-001)

[2]

Chi-Chou Kao* and Yu-Ming Lin, “Design of Embedded Sensor System Based on Parallel Reconfigurable Computing Platform,” Symposium on Digital Life Technologies (DLT), SS19-01 (2016 June 18-19, Pingtung, Taiwan). (MOST 103-2622-E-024-006-CC3)

[3]

Chi-Chou Kao* and Zhe-Han Lo, “Implementation of Stereoscopic Image Generation,”  Symposium on Digital Life Technologies (DLT), SS19-02 (2016 June 18-19, Pingtung, Taiwan). ( MOST 104-2221-E-024-001)

[4]

Chi-Chou Kao*, “E-Health Design of EEG Signal Classification for Epilepsy Diagnosis,” International Symposium on Biometrics and Security Technologies (ISBAST), pp. 67–71 (2013 July 2-5, Chengdu, Sichuan China). (EI, NSC 101-2221-E-024-017)

[5]

Chi-Chou Kao* and Kun-Cte Lin, “Clock Skew Minimization with Adjustable Delay Buffers Restriction,” International Symposium on Next-Generation Electronics (ISNE 2013), pp. 321–324 (2013 February 25-26, Kaohsiung, Taiwan). (EI, NSC 101-2221-E-024-020)

[6]

Chi-Chou Kao*, Yen-Tai Lai, and Chao-Feng Tseng, “Laplacian-Based H.264 Intra-Prediction Mode Decision,” International ICST Conference on Communications and Networking in China (CHINACOM), pp. 638–641 (2012 August 7, Kunming, China). (EI, NSC 100-2221-E-024-010)

[7]

Jun-Hao Wang, and Chi-Chou Kao*, “Adjustable Delay Buffers Assignment Algorithms for Clock Skew Minimization,” Information Technologies Applications and Management Conference (ITAMC), ITAMT119 (2012 May 25, Kaohsiung, Taiwan) (NSC 100-2221-E-024-010)

[8]

Yi-Ciang Lin, and Chi-Chou Kao*, “Improved Snoop Protocol to Reduce Power in MPSoC,” Workshop on Computer Architectures, Embedded Systems and VLSI/EDA, National Computer Symposium (CEV-NCS), pp. 28–35 (2011 December 2~3, Chiayi, Taiwan). (NSC 100-2221-E-024-010)(nominated as Best Paper)

[9]

Chi-Chou Kao*, “View Based Rotation Invariant 3D Shape Retrieval,” International Conference on Remote Sensing and Data (ICRSD), pp. 150–155 (2011 July 2~3, Tsin Shui Wai, New Territories, Hong Kong, China). (NSC 99-2221-E-024-008)

[10]

Chi-Chou Kao*, Jun Wu, and Shih-Chieh Chen, “Energy Efficient Clustering Communication Protocol for Wireless Sensor Network,” International Conference on Advanced Communication Technology (ICACT), pp. 830–833 (2010 February 7~10, Phoenix Park Gangwon-Do, Seoul, Republic of Korea). (EI, NSC 98-2221-E-024-005, ISBN: 978-89-5519-146-2)

[11]

Yen-Tai Lai, Chia-Nan Yeh, and Chi-Chou Kao*, “A Novel Digital Pixel Sensor System,” Proceedings of 2009 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2297–2300 (2009 May 24~27, Taipei, Taiwan). (EI, EDU E-51-029, ISSN: 0271-4310)

[12]

Hung-Yi Lin*, Yen-Tai Lai, and Chi-Chou Kao, “A Simple Scheme to Extend the Linearity of the Continuous-Time CMFB Circuit for Fully-Differential Amplifier,” IEEE TENCON 2008, Session O21 Analog and Mixed Signal Circuits, 1569130755 (2008 November 18~21, University of Hyderabad, Hyderabad, India). (EI, NSC 97-2221-E-024-016, ISBN: 978-1-4244-1272-3)

[13]

Chi-Chou Kao*, Chia-Nan Yeh, Yen-Tai Lai, and Tang-Wei Liao, “A New Cluster Head Assignment Algorithm for Low Energy Clustering Communication Protocols in Wireless Sensor Network,” International Conference on Communications, Circuits and Systems (ICCCAS), pp. 365–368 (2007 July 11~13, Kitakyushu, Japan). (EI)

[14]

Chi-Chou Kao*, “Crosstalk Minimization Method for System-on-Chip,” International Conference on Communications, Circuits and Systems (ICCCAS), pp. 1181–1184 (2007 July 11~13, Kitakyushu, Japan). (EI, ISBN: 0-7803-9015-6)

[15]

Yen-Tai Lai, Chia-Nan Yeh, and Chi-Chou Kao*, “A Novel Flash A/D Converter with Ultra Short Latency and High Bubble Error Tolerance,” International Conference on Communications, Circuits and Systems (ICCCAS), pp. 1048–1052 (2007 July 11~13, Kitakyushu, Japan). (EI, ISBN: 0-7803-9015-6)

[16]

Chi-Chou Kao*, Tzu-Chiang Tai, Yun-Yi Hwang, and Yen-Tai Lai, “A Sequential Circuit Partitioning Algorithm for Dynamically Reconfigurable FPGAs,” International Conference on Communications, Circuits and Systems (ICCCAS), pp. 1185–1188 (2007 July 11~13, Kitakyushu, Japan). (EI, ISBN: 0-7803-9015-6)

[17]

Yen-Tai Lai, Tzu-Chiang Tai, Chi-Chou Kao*, and Chung-Kai Liu, “An Improved Architecture for Optimizing Partitioning Cost of Time-Multiplexed FPGA,” IASTED International Conference on Circuits, Signals, and Systems, pp. 94–98 (2007 July 2~4, Banff, Alberta, Canada). (NSC 95-2221-E-251-004, ISBN:978-0-88986-670-6)

[18]

Chi-Chou Kao*, Chih-Chiang Tzeng, and Yen-Tai Lai, “An Optimal Power Algorithm for Interface Design of System-on-Chip,” IASTED International Conference on Circuits, Signals, and Systems, pp. 31–34 (2007 July 2~4, Banff, Alberta, Canada). (ISBN:978-0-88986-670-6)

[19]

Chi-Chou Kao*, “A Fast Fine Granularity Scalable Coding for Video Streaming,” International Conference on Systems and Signals (ICSS), pp. 453–456 (2005 April 28~29, Kaohsiung, Taiwan)

[20]

Chi-Chou Kao*, Tzu-Chiang Tai, and Yen-Tai Lai, “A Communication Cost Minimization Algorithm for Dynamically Reconfigurable FPGA,” International Conference on Systems and Signals (ICSS), pp. 1059–1062 (2005 April 28~29, Kaohsiung, Taiwan). (NSC 93-2215-E-251-001)

[21]

Yen-Tai Lai, Chi-Chou Kao*, Yung-Chuan Jiang, and Hsing-Chuang Chen, “An Efficient Video Segmentation Algorithm Based On Accumulative Information Technique,” International Conference on Systems and Signals (ICSS), pp. 449–452 (2005 April 28~29, Kaohsiung, Taiwan)

[22]

Chi-Chou Kao* and Yen-Tai Lai, “An Efficient Speech Enhancement Method Using Kalman Filter and Spectral Subtraction,” IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), pp. 181–184 (2004 December 6~9, Tainan, Taiwan). (EI, ISBN: 0-7803-7690-0)

[23]

Yen-Tai Lai, Yung-Chuan Jiang*, and Chi-Chou Kao, “DTA: Layout Design Tool for CMOS Analog Circuit,” IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), pp. 537–540 (2004 December 6~9, Tainan, Taiwan). (EI, ISBN: 0-7803-7690-0)

[24]

Ming-Hui Chan, Chi-Chou Kao*, and Shih-Hwei Tang, “Design and Implementation of Interactive E-Learning System,” 2004 Symposium on Digital Learning, pp. 674–683 (2004 April 28, Pingtung, Taiwan)

[25]

Chi-Chou Kao* and Yen-Tai Lai, “Area-Minimal Algorithm for LUT-Based FPGA Technology Mapping with Duplication-free Restriction,” Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 717–722 (2004 January 27~31, Yokohama, Japan). (EI, NSC 92-2218-E-251-001, ISBN: 0-7803-8175-0)

[26]

Chi-Chou Kao* and Yen-Tai Lai, “A Technology Mapping Algorithm for Heterogeneous FPGAs,” Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 213–216 (2003 January 21~24, Kitakyushu, Japan). (EI, ISBN: 0-7803-7659-5)

[27]

Yen-Tai Lai, Chi-Chou Kao*, and Hao-Jan Chen, “Design and Implementation of an Adaptive FIR Filter based on Delayed Error LMS Algorithm,” 1999 IEEE Workshop on Signal Processing Systems (SiPS) Design and Implementation, pp. 704–712 (1999 October 20~22, Taipei, Taiwan). (EI, ISSN: 1520-6130)

[28]

Chi-Chou Kao* and Yen-Tai Lai, “A Routability and Performance Driven Technology Mapping Algorithm for LUT Based FPGA Designs,” Proceedings of 1999 IEEE International Symposium on Circuits and Systems (ISCAS), Vol. 1 pp.474–477 (1999 May 30~June 2, Orlando, Florida, U.S.A.). (EI, ISSN: 0271-4310)

[29]

Yen-Tai Lai, Chi-Chou Kao*, and Wu-Chien Shieh, “A Quadratic Programming Method for Interconnection Crosstalk Minimization,” Proceedings of 1999 IEEE International Symposium on Circuits and Systems (ISCAS), Vol. 6 pp. 270–273 (1999 May 30~June 2, Orlando, Florida, U.S.A.). (EI, ISSN: 0271-4310)

[30]

Yen-Tai Lai, Chi-Chou Kao*, Tsun-Chen Chang, and Kun-Nern Chen, “A Field Programmable Gate Array Chip with Hierarchical Interconnection Structure,” Proceedings of 1998 IEEE International Symposium on Circuits and Systems (ISCAS), Vol. 2 pp. 402–405 (1998 June 1~3, Monterey, California, U.S.A.). (EI, ISSN: 0271-4310)

Books

[1]

高啟洲譯,20101月初版,應用數值方法-使用MATLAB”,滄海圖書資訊公司(ISBN: 978-986-157-660-2)。原著:Steven. C. Chapra, 2008, “Applied Numerical Methods with MATLAB for Engineers and Scientists,” 2nd Ed. Mc Graw Hill.

[2]

Chi-Chou Kao, July, 2016, “Technology Mapping for Lookup-Table Based FPGAs”, Golden Light Academic Publishing (ISBN: 978-3-639-82633-3).

Patents

專利類別

專利名稱

專利國家

專利號碼

專利期間

專利發明人

專利權人

新型專利

平行計算的嵌入式感測系統

台灣

M515677

201601~
202509

高啟洲

高啟洲

新型專利

立體嵌入式影像系統

台灣

M529333

201609~
202606

高啟洲

高啟洲

 

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